1. Field of the Invention
The present invention relates in general to charge pump, and more particularly to charge pump which experiences no charge feedthrough phenomenon during switching period.
2. Description of the Related Art
Charge pump is commonly utilized in phase-locked loops (PLL) to control a voltage applied to a voltage controlled oscillator (VCO). Therefore, charge pump is an important component of PLL as charge pump in many ways determines the maximum range and accuracy of lock frequencies for PLL. Further, charge pump may require a significant amount of semiconductor die space to implement and relatively high voltages to operate, thus increasing the overall size and power consumption of PLL. With the ever-increasing performance of microprocessors, much more stringent requirements have been placed on the design of phase-locked loop, and hence on the design of charge pump circuit. FIG. 1 shows a prior art phase-locked loop (PLL) 100 as generally comprising a phase detector 1 10, a charge pump 120, a loop filter 130, a voltage controlled oscillator 140, a frequency divider 150, a frequency divider 160, and a reference clock generator 170.
Phase detector 110 compares a reference input signal REF.sub.-- IN, which may be provided by the reference clock generator 170 via the frequency divider 160, with a signal VCO.sub.-- IN, which VCO 140 generates via the frequency divider 150. The phase detector 110 provides the control signals CNTRL.sub.-- P and CNTRL.sub.-- N for the transistors 122 and 128 of the charge pump 120, respectively. When the signal REF.sub.-- IN and the signal VCO.sub.-- IN are in phase, phase-locked loop 100 is locked, and the control signals CNTRL.sub.-- P and CNTRL.sub.-- N have matched duty cycles, phases, and frequencies.
The Charge pump 120 responds to the control signals CNTRL.sub.-- P and CNTRL.sub.-- N from the phase detector 110 and outputs a current Ic to the loop filter 130, which generally includes a large capacitor and averages the current Ic, to generate a DC voltage at the input of VCO 140. The loop filter 130 filters out the noise in the input signal to the filter 130.
In other words, voltage Vout depends on the current Ic to the loop filter 130. The current Ic, which is output at the node 125, is the difference between an up-current, Ip, into a node 125 and a down-current, In, out of the node 125. A transistor 122 turns on or off a current source 124 that supplies Ip and charges the node 125 and increases the voltage Vout. A transistor 128 turns on or off a current source 126 that supplies down-current, In, and discharges the node 125 and decreases the voltage Vout. Filter 130 reduces the output voltage fluctuations caused by switching of Ip and In. Ip and In should be equal to maintain a constant output voltage Vout and a constant frequency oscillation signal f.sub.vco from VCO 140. Otherwise, if the signal REF.sub.-- IN and the signal VCO.sub.-- IN are not in phase, the phase detector 110 changes the duty cycles of control signals CNTRL.sub.-- P and CNTRL.sub.-- N respectively to change the voltage Vout and change the frequency of oscillation of signal f.sub.vco from the VCO 140. For example, when the signal VCO.sub.-- IN trails the reference input signal REF.sub.-- IN, the duty cycle of control signal CNTRL.sub.-- P is increased relative to the duty cycle of control signal CNTRL.sub.-- N. The increased duty cycle increases the duration of Ip, charges the node 125, increases the voltage Vout, and increases the oscillation frequency of signal f.sub.vco from VCO 140.
Traditionally, in a CMOS charge pump, the transistor 122 and current source 124 are P channel devices because P channel transistors handle the supplied voltage Vdd better, and the transistor 128 and current source 126 are N channel devices because N channel devices handle the reference voltage Vss better. In FIG. 1, there is problem with regard to the current feedthrough issue but the noise immunity capability is better.
As aforementioned, currents Ip and In increase and decrease in response to the control signals in a manner characteristic of P channel devices 122 and 124 and N channel devices 126 and 128 respectively. However, it is not likely to have a perfect match response of P channel devices and N channel devices. For example, even when the phase detector 110 provides control signals of equal duty cycle to the transistors 122 and 128, a net current Ic flows to the node 125 and increases the voltage Vout. VCO 140 would then be driven to oscillate faster, and the signal VCO.sub.-- IN becomes out of phase with the reference signal REF.sub.-- IN. Phase detector 110 would in turn change the control signals CNTRL.sub.-- P and CNTRL.sub.-- N and decreases voltage Vout until signals VCO.sub.-- IN and REF.sub.-- IN are in phase again. Once signals VCO.sub.-- IN and REF.sub.-- IN are in phase, the control signals CNTROL.sub.-- P and CNTRL.sub.-- N are of equal duty cycle, and voltage Vout rises again as described above. Voltage increases and decreases repeatedly in this manner causing jitters in the signal f.sub.vco provided by VCO 140.
Furthermore, the charging and discharging current are controlled by one corresponding switch. Thus, the charging or discharging current is turned off when the corresponding switch is off. Thereafter, when the charging or discharging is turned on by the corresponding switch, a charge feedthrough will occur and the switching speed is slowed down to stabilize the charging or discharging current. This in turn causes a significant fluctuation of the output voltage Vout as shown in FIG. 2(a). Besides, the duty cycle of the output waveform is not going to be a desired 50% as shown in FIG. 2(b). The jitters and the unbalanced output waveform may be unacceptable in applications where a precise timing or a high-frequency clock signal is a demand.
Referring to a prior art of "A low jitters 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3V/5V Operation" by Howard C. Yang et al., on IEEE Journal of Solid State Circuits, 1997, there are two switches to control the charging current and another two switches to control the discharging current. Therefore, the charging and discharging currents of Howard C. Yang et al. can always be kept on, and the circuit can work smooth at high speed. However, Howard C. Yang et al. make use of a current-steering amplifier (CSA) to keep the output voltage of charging/discharging device at the same voltage level, which results in a complex circuit and demands a larger chip area.